元器件交易网讯 4月23日消息，据外媒报道，Altera发布具有硬浮点的全新Arria 10 FPGA，但其具体设计流程还需要等待。

　　其中，DSP模块符合IEEE 754标准，该模块也将用于Stratix 10 FPGA中。

　　Arria运算能力达到1.5Tflop，Stratix运算能力为10Tflop。

　　“设计者可以选择固定模式或浮点模式，且浮点块可以与已有设计向后兼容。用户可以采用这些FPGA解决大数据分析、制作油气业抗震模型、进行金融模拟。”

　　浮点模块采用的包括示范和基准在内的浮点设计流程将于下半年推出。

　　20nm的Arria 10采用两枚ARMCortex-A9核心，串行收发器速度达28.3Gbit/s，母板最高支持17.4Gbit/s，并支持2.666Gbit/s DDR4。（元器件交易网毛毛  译）

　　以下为原文：

　　Altera adds hard floating point to FPGAs

　　Altera is shipping Arria 10 FPGAs withhardened floating-point DSP blocks, but customers will have to wait for designflows.

　　The DSP block, which is IEEE 754-compliant,will also be in Stratix 10 FPGAs.

　　Up to 1.5 Tflop is claimed in Arria and 10Tflop in Stratix.

　　“Designers are able to choose either fixed or floating-point modesand the floating point blocks are backwards compatible with existing designs,”said Altera. “The inclusion enable customers to use FPGAs to address problemsin big data analytics, seismic modeling for oil and gas industries andfinancial simulations.”

　　Floating-point design flows, includingdemonstrations and benchmarks, for the floating-point blocks will be availablein the second half of this year.

　　“Customers can start designing today with Arria 10 FPGAs using softimplementations of floating point and then seamlessly migrate to hardenedfloating point implementation when the design flows are available.”

　　The firm’s DSP Builder Advanced Blocksetwill offer a model-based design flow allowing designers to go from systemdefinition and simulation to system implementation using MathWorks Simulink.

　　20nm Arria 10 can also include a dual-corehard ARM Cortex-A9, serial transceivers up to 28.3Gbit/s, backplane support upto 17.4Gbit/s, and support for DDR4 at 2.666Gbit/s.